The present invention relates to semiconductors, and more particularly relates to the structure of vias in semiconductor substrates and to processes for forming such vias.
Numerous structures used in the electronics industry incorporate semiconductor bodies. Such semiconductor bodies commonly are provided as planar structures having oppositely facing major surfaces. In a common semiconductor chip, the semiconductor body is provided with active semiconductor elements at or near a first one of the major surfaces. The active semiconductor elements typically include doped semiconductor materials deposited on or formed in the body, as well as electrically conductive structures serving as electrodes of the devices. Other electrically conductive structures extend in directions parallel to the plane of the first major surface, commonly referred to as the “X” and “Y” directions. These conductive structures form interconnections between the various semiconductor elements, as well as contacts used to connect the devices to external circuits. These structures may be provided in plural layers overlying one another at or near the first major surface of the semiconductor body.
In some cases, as chip may incorporate openings or “vias” extending through the body in the directions perpendicular to the major surfaces of the semiconductor body, commonly referred to as the “vertical” or “Z”-direction. Such vias commonly are referred to as “through silicon vias.” Through silicon vias typically are provided with conductive elements which connect circuit elements on or adjacent the first major surface with contacts on or adjacent the opposite major surface. In this arrangement, external connections can be made to the chip on the opposite major surface in addition to or in lieu of external connections on the first major surface.
The via structure typically includes a dielectric layer lining the opening in the semiconductor body and the conductive element, most commonly formed from a metal, inside the lined opening. The dielectric layer serves to electrically isolate the conductive element from the semiconductor body itself. Where the semiconductor body is formed from silicon, the dielectric can be formed by treating the interior surface of the via at high temperature in an oxidizing environment typically with oxygen, water vapor or both, so as to convert silicon at and near the interior surface into silicon dioxide, which serves as the dielectric. In other cases, a dielectric layer can be deposited in the opening by plasma enhanced chemical vapor deposition (“PECVD”).
Other semiconductor substrates are used as interconnection elements in electronic circuitry as, for example, as elements interconnecting chips with larger circuit panels, such as circuit boards, or as elements interconnecting multiple chips with one another. These semiconductor substrates may or may not include active circuit elements, but include electrically conductive elements and dielectric materials insulating the various conductive elements from one another. The conductive elements may be disposed on one or both surfaces of the body. These structures also may incorporate vertically vias extending through the body and conductive elements within such vias.
It is desirable to make the via structures with the smallest possible diameter consistent with other requirements. Great efforts have been devoted in the semiconductor art towards miniaturizing the active circuit elements and conductive structures used on semiconductor chips and other semiconductor bodies so as to pack ever more elements onto the available space, and thus increase the processing power and speed of the circuitry. For example, in modern semiconductor chips, active elements and conductive elements have dimensions in the X- and Y-directions measured in nanometers or microns. Thus, a via which is a few microns in diameter will occupy space that would otherwise be available for tens or hundreds of other elements.
Using specialized anisotropic etching processes, it is possible to form openings in semiconductor bodies having diameters as large as desired, and as small as about 1 micron or less at etch rates up to about 10-20 microns of via depth per minute. One example of such an anisotropic etching process is a species of reactive ion plasma etching process commonly referred to as the Bosch process. However, the available processes for forming openings in silicon and other substrates leave the openings with extremely rough interior surfaces, particularly when these processes are operated at high etch rates.
If the silicon at the interior surface of the opening is treated to convert it into silicon dioxide, the silicon dioxide dielectric will have a correspondingly rough surface. This rough surface will cause difficulties in depositing metal into the lined opening. The rough surface typically has undercut features that are difficult to fill with the metal. Moreover, the exterior surface of the conductive element, at the interface between the conductive element and the dielectric, will be a rough, jagged surface. The jagged surface of the conductor impairs the ability of the conductor to transmit signals at the frequencies used in certain electronic circuits as, for example, at hundreds of MHz or above. This phenomenon is related to the “skin effect”, which concentrates high-frequency signals nears the surface of the conductor. If the conductor has a rough surface, the signals are degraded. The jagged surface of the interface between the conductor and the dielectric layer also concentrates electrical charges, which can lead to high leakage of electrical signals through the dielectric layer to the semiconductor body. Further, the jagged surface at the interface between the metal and the dielectric acts to concentrate mechanical stresses in the structure. Such mechanical stresses can arise, for example, when the structure is subjected to temperature changes and the metal in the conductor expands or contracts at a different rate than the silicon body. Concentrated stresses of this nature can cause the structure to fail during use.
The problems associated with the rough interior surfaces of the openings can be alleviated to some extent by reducing the etching rate in the process used to form the openings. However, this reduces productivity and increases the cost. Moreover, it does not fully eliminate the surface roughness in the openings.
Another approach that can be employed to reduce surface roughness is to prolong the process used to convert silicon to silicon dioxide at the interior surfaces of the openings, and thus form a very thick layer as, for example, one to three microns in thickness, at the interior surface of the opening. This thick oxide layer is then etched away until the layer is substantially removed. The etching process that removes the silicon dioxide tends to leave a smoother surface. This smoother surface is then treated again to form a further layer of silicon dioxide dielectric. However, this process requires prolonged exposures to the oxidizing atmosphere at elevated temperature, and thus is expensive. Moreover, this process effectively increases the diameter of the opening. Stated another way, the opening after etching away the thick silicon dioxide layer has a diameter equal to the original interior diameter of the opening plus twice the thickness of the silicon dioxide that is removed during the etching process. This partially defeats the purpose of forming a small opening in the first place.
Accordingly, despite substantial efforts in the art heretofore, further improvement would be desirable.